Cache memory system, a cache memory, an updating method for the cache memory and for the cache memory system, and an updating program for the cache memory system

ABSTRACT

A cache memory system includes a cache memory having a plurality of entries. Each entry configured to include each of information storage units fetching and storing part of information stored in a main memory. Each of reference bit storage units stores a use status for a certain period of information stored in the corresponding information storage unit. A hit detection circuit is connected to the information storage units. The hit detection circuit generates a hit signal to each of the reference bit storage units.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom prior Japanese Patent Application P2003-65192 filed on Mar. 11,2003; the entire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a cache memory system, andspecifically, to an updating method and an updating program for a cachememory system.

[0004] 2. Description of the Related Art

[0005] Cache memories currently used in a microprocessor and the like,in which address translation information and data are stored, areconfigured to store a plurality of sets of information that are a partof information stored in a main memory. A cache memory storing theaddress translation information is called an address cache or aTranslation Look-aside Buffer (TLB). A cache memory storing the data iscalled a data cache. A unit of a storage area storing a set ofinformation is referred to as “entry.” The cache memories themselvescannot store all the information required for CPU processing thatconstitutes a computer system. Therefore, it is necessary to fetch newinformation from the main memory and update the cache memories.

[0006] There are various methods for storing the address translationinformation of the TLB or the data cache in the cache memory itself andfor utilizing the same. As for a cache memory having a fully associativeconstitution, a method for randomly selecting an entry is employed inorder to prevent a complex circuit design.

[0007] However, in terms of frequency of usage, there are entries thatshould be updated in each set of entry information in a cache memorysince such entries are less frequently used. On the other hand, thereare entries that are inappropriate for updating since they are morefrequently used. With the method for randomly selecting an entry, thereis a possibility that the more frequently used entries are updated.

[0008] Thus, the entry information that has been updated must bereregistered. As a result of performing the operation of reregisteringentry information, time efficiency is reduced, and performance isdegraded.

[0009] In the case of the fully associative cache memory, for selectingthe updating entry, the method for selecting the random entry is used toavoid complication of the circuit design. Accordingly, there is apossibility that the more frequently used entry is updated.

SUMMARY OF THE INVENTION

[0010] In order to solve the above problems, a first aspect of thepresent invention inheres in a cache memory having a plurality ofentries, wherein each of the entries includes an information storageunit configured to fetch and store a part of the information stored in amain memory and a reference bit storage unit configured to store a usestatus for a certain period of information stored in the informationstorage unit.

[0011] A second aspect of the present invention inheres in a cachememory system including a cache memory having a plurality of entries,each of the entry includes an information storage unit configured tofetch and store a part of the information stored in a main memory and areference bit storage unit configured to store a use status for acertain period of information stored in the corresponding informationstorage unit, and a hit detection circuit connected to the informationstorage units, the hit detection circuit configured to generate a hitsignal to each of the reference bit storage units.

[0012] A third aspect of the present invention inheres in an updatingmethod for a cache memory, having a plurality of segments, one segmentincluding a unit of a plurality of entries. The updating method includessending reference bits accompanying the respective entries fromreference bit storage units into a processing circuit and generating theposition number of a selected entry and an unused entry presence signaland performing entry shuffle by repeatedly rotating the plurality ofentries and generating the position number of the selected entry and theunused entry presence signal.

[0013] A fourth aspect of the present invention inheres in an updatingmethod for a cache memory system including a process of sending ageneration alternation signal from an interval timer to a reference bitstorage unit storing a reference bit, a process of determining whetherthe number of hit entries is larger than an upper boundary hit numberset in an upper boundary hit number register, a process of determiningwhether the number of hit entries is smaller than a lower boundary hitnumber set in a lower boundary hit number register when the number ofhit entries is not larger than the upper boundary hit number, a processof shortening a period of the interval timer when the number of hitentries is larger than the upper boundary hit number, and a process oflengthening the period of the interval timer when the number of hitentries is smaller than the lower boundary hit number.

[0014] A fifth aspect of the present invention inheres in an updatingprogram for a cache memory system to be executed by a cache memorysystem configured to include an unused entry detection block connectedto a reference bit storage unit constituting a cache memory, an intervaltimer, an upper boundary hit number register connected to the unusedentry detection block; and a lower boundary hit number register. Theupdating program for a cache memory system includes an instruction tosend a generation alternation signal from the interval timer to thereference bit storage units, an instruction to determine whether thenumber of hit entries is larger than an upper boundary hit number set inthe upper boundary hit number register, an instruction to determinewhether the number of hit entries is smaller than a lower boundary hitnumber set in the lower boundary hit number register when the number ofhit entries is not larger than the upper boundary hit number; aninstruction to shorten a period of the interval timer when the number ofhit entries is larger than the upper boundary hit number, and aninstruction to lengthen the period of the interval timer when the numberof hit entries is smaller than the lower boundary hit number.

[0015] A sixth aspect of the present invention inheres in an updatingprogram product stored on a memory medium of a cache memory system to beexecuted by a cache memory system configured to include an unused entrydetection block connected to a reference bit storage unit constituting acache memory, an interval timer, an upper boundary hit number registerconnected to the unused entry detection block, and a lower boundary hitnumber register. The updating program includes an instruction to send ageneration alternation signal from the interval timer to the referencebit storage unit; an instruction to determine whether the number of hitentries is larger than an upper boundary hit number set in the upperboundary hit number register, an instruction to determine whether thenumber of hit entries is smaller than a lower boundary hit number set inthe lower boundary hit number register when the number of hit entries isnot larger than the upper boundary hit number, an instruction to shortena period of the interval timer when the number of hit entries is largerthan the upper boundary hit number, and an instruction to lengthen theperiod of the interval timer when the number of hit entries is smallerthan the lower boundary hit number.

BRIEF DESCRIPTION OF DRAWINGS

[0016]FIG. 1 is a block diagram schematically showing a cache memorysystem according to the first embodiment of the present invention, whichis a block diagram showing a connection relationship between the cachememory system and a main memory.

[0017]FIG. 2 is a block diagram showing the cache memory systemaccording to the first embodiment of the present invention, which is ablock diagram including a connection relationship between the cachememory and an interval timer.

[0018]FIG. 3 is a schematic diagram showing variation of internal statusvalues of the first reference bit RA and the second reference bit RB dueto a generation alternation signal IS from the interval timer and aperiod TI of the interval timer.

[0019]FIG. 4 is a schematic diagram showing changes and operations ofthe internal status values of the first reference bit RA and the secondreference bit RB in an example wherein an entry is hit twice by entryhits Hit1 and Hit2.

[0020]FIG. 5 is a block diagram showing a reference bit judgementcircuit and peripheral circuits thereof that constitute the cache memorysystem according to the first embodiment of the present invention, whichshows an example wherein a use status storage unit includes a 2-bitregister, a 4-bit register and a 2-bit counter.

[0021]FIG. 6 shows one of other examples wherein the use status storageunit includes the 2-bit register and the 4-bit register.

[0022]FIG. 7 shows one of other examples wherein the use status storageunit includes the 2-bit register and the 2-bit counter.

[0023]FIG. 8 shows one of other examples wherein the use status storageunit includes the 4-bit register and the 2-bit counter.

[0024]FIG. 9 is a schematic diagram showing a dividing method ofdividing into eight segments, each being composed of eight entries, inthe case where the cache memory is composed of 64 entries.

[0025]FIG. 10 is a block diagram schematically showing hardware in asegment constituting the cache memory in the cache memory systemaccording to the first embodiment of the present invention.

[0026]FIG. 11 is a schematic diagram showing processing in a segment 0,which illustrates the status before rotation in entry shuffle in asegment to be updated.

[0027]FIG. 12 is a schematic diagram illustrating the status of therotation in the entry shuffle in the segment to be updated.

[0028]FIG. 13 is a schematic diagram illustrating the status after therotation in the entry shuffle in the segment to be updated.

[0029]FIG. 14 is a block diagram schematically showing the entirehardware for eight segments constituting the cache memory according tothe first embodiment of the present invention.

[0030]FIG. 15 is a schematic diagram showing the entiresegment-processing, which illustrates the status before the rotation.

[0031]FIG. 16 is a schematic diagram illustrating the status of therotation in the entire segment processing.

[0032]FIG. 17 is a schematic diagram illustrating the status after therotation in the entire segment processing.

[0033]FIG. 18 is a schematic diagram illustrating a constitution todetermine an entry number EN.

[0034]FIG. 19 is a schematic diagram illustrating a processing flow on atime axis for updating of the entry and execution of shuffle.

[0035]FIG. 20 is a block diagram schematically illustrating supply of ashuffle signal to the segment.

[0036]FIG. 21 is a block diagram schematically showing a cache memorysystem according to a second embodiment of the present invention, whichis an entire block diagram including the cache memory and a countcontrol mechanism for the interval timer.

[0037]FIG. 22 is a flow chart based on a determination algorithm in anunused entry detection block constituting the cache memory systemaccording to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] Various embodiments of the present invention will be describedwith reference to the accompanying drawings. It is to be noted that thesame or similar reference numerals are applied to the same or similarparts and elements throughout the drawings, and the description of thesame or similar parts and elements will be omitted or simplified.

[0039] In the following descriptions, numerous specific details are setforth such as specific signal values, etc. to provide a thoroughunderstanding of the present invention. However, it will be obvious tothose skilled in the art that the present invention may be practicedwithout such specific details. In other instances, circuits well-knownhave been shown in block diagram form in order not to obscure thepresent invention in unnecessary detail.

EMBODIMENTS

[0040] The first and second embodiments shown below exemplify anapparatus or a method for embodying technical ideas of the presentinvention. The technical ideas are not intended to be limited bystructures, arrangements, or the like of the components described below.Various modifications can be added to the technical ideas of the presentinvention within the scope of claims.

[0041] In the embodiments of the present invention, as shown in FIG. 1,a “cache memory system” 50 is a system including a cache memory 8 as apart of components thereof. Specifically, the cache memory system 50includes a semiconductor integrated circuit composed of the cache memory8 and peripheral circuits thereof or a processor 30. Alternatively, thecache memory system 50 includes a digital signal processor, a customLSI, a timer LSI, or the like. The cache memory 8 is supplied withinformation from a main memory 60 which is an external main memory.

[0042] In the “fully associative system,” information can be written orstored in any entries without limitation. Specifically, the “fullyassociative system” does not employ a method of selecting an updatingentry in accordance with a rule of some kind by use of part ofinformation contained in address information and writing information inthe selected entry. In the embodiments of the present invention, the“cache memory system” includes a cache memory having a fully associativeconstitution or a similar constitution built-in or externally attachedthereto, where the cache memory 8 is an address cache or a data cache.The cache memory system has a function to receive and hold usagehistories of the respective entries constituting the cache memory bygeneration management using a timer and to select an unused entry whenupdating the contents of the cache memory with new information.

[0043] Moreover, in order to efficiently perform the function describedabove, the “cache memory system” of the present invention has a functionto automatically adjust a period of the timer by utilizing andevaluating the usage histories of the respective entries.

[0044] In the embodiments of the present invention, a description willbe given of a cache memory system, a cache memory, an updating methodfor the cache memory and for the cache memory system, and an updatingprogram for the cache memory system, in which an updating entry can beautomatically selected from unused entries therefore providing efficientuse of time, software does not need to repeat the setting of the periodof the timer frequently, and the period of the timer can beautomatically adjusted.

First Embodiment

[0045] As shown in FIG. 2, the cache memory system 50 according to thefirst embodiment of the present invention includes a cache memory 8, ahit detection circuit 5, a control register 4, an interval timer 3,reference bit storage units 31 storing a reference bit R and a processor30. As shown in FIG. 2, the cache memory 8 includes information storageunits 1 each corresponding to one of n entries from an entry 0 to anentry n-1 and reference bit storage units 31 storing n reference bits Raccompanied with the respective information storage units 1.Specifically, as shown in FIGS. 9 and 14 described later, the cachememory 8 is composed of a plurality of segments, and each of thesegments is composed of the plurality of entries. Each of the entriesincludes one of the information storage units 1 and one of the referencebit storage units 31. Each reference bit storage unit 31 includes a usestatus storage unit 2, a reference bit judgement circuit 6, and aselected reference bit storage unit 32 storing a selected reference bitRS. The use status storage unit 2 includes a first reference bit storageunit 37 storing a first reference bit RA and a second reference bitstorage unit 38 storing a second reference bit RB. The hit detectioncircuit 5 compares cache address information CA generated from each ofthe information storage units 1 in the entries 0, 1, . . . , n-2, andn-1 of the cache memory 8 to processor cache access address informationPA generated from the processor 30. The hit detection circuit 5generates a hit signal HT to one of the reference bit storage units 31.A control information CI generated from the control register 4 is sentto the interval timer 3. The interval timer 3 supplies a generationalternation signal IS for the first reference bit storage unit 37 andthe second reference bit storage unit 38 in the use status storage unit2 and a reference bit judgement circuit 6. Note that, in FIG. 2, adescription of components described later in FIGS. 10 to 17 such aspriority encoders 10A and 10B and processing circuits 12A and 12B isomitted.

[0046] First, a description is given of the cache memory 8 of the fullyassociative system including n entries. In the “fully associativesystem,” information can be written or stored in any entries withoutlimitation. Specifically, the “fully associative system” does not employa method of selecting an updating entry in accordance with a rule ofsome kind by use of part of the information contained in the addressinformation and writing information in the selected entry. On the otherhand, regardless of the constitution such as the fully associativesystem or a non-fully associative system, a memory capacity of the cachememory built in the processor is generally small. Accordingly, thememory capacity of the cache memory is less than an amount ofinformation that is wanted or required to be stored. In recent years,since operating frequency of the processor has been dramaticallyincreased, time loss in data transmission and reception between theprocessor and the memory which has a large capacity and is externallyconnected to the processor has become a problem. However, the cachememory plays an important role in reducing the generated time loss by ahigh speed operation thereof.

[0047] Meanwhile, the cache memory itself has a limitation in the memorycapacity and does not have a sufficient capacity to store information.Accordingly, contents of the cache memory itself must be often updated.To update the contents, the updating entry is selected by using variousalgorithms depending on the constitution of the cache memory.

[0048] Generally, in the non-fully associative cache memory, forexample, in the n-way set associative cache memory, even if a largenumber of entries are included, the number of the entries to be judgedis reduced when judging whether the entry should be updated. Comparedwith the non-fully associative system, all, or a large number of entriesneed to be targeted for examination in the case of the fully associativesystem.

[0049] However, in this case, if an algorithm (e.g., Least Recently Used(LRU)) employed in the non-fully associative system is employed, thecircuit itself becomes very complicated and enormous, thus adverseeffects on improvement are imposed on the operating speed of theprocessor. Therefore, in the fully associative cache memory, the methodof randomly selecting the updating entry has been employed.

[0050] However, in this method of randomly selecting an updating entry,there is a possibility that a more frequently used entry that isscheduled to be used in the future may be updated. If the entryscheduled to be used in the future were updated, the performance wouldbe degraded.

[0051] The reference bit storage unit 31 is a register storing a usestatus, in other words, a hit status for a certain past period. For asimple reference bit storage unit 31, the register is composed of twobits and stores a use status “used (hit)/unused (miss)” for a certainpast period. The selected reference bit RS is information generated froma register in the use status storage unit 2 through the reference bitjudgement circuit 6, whereby the register stores the numbers of times oftranslation for certain current and past periods. The selected referencebit RS is stored in the selected reference bit storage unit 32.

[0052] Herein, a dedicated timer is used to examine the use status for acertain period. First, a description will be given of an example of amethod of narrowing down the options of the unused entries by usinginformation called reference bits R, which store the usage historyinformation of each entry for a certain period by use of the timer.

[0053] The reference bits R to be stored in the reference bit storageunits 31 are in the respective entries 0, 1 . . . , n-2, and n-1 of thecache memory 8. Each of the reference bits R is the informationindicating a status of whether the corresponding entry 0, 1 . . . , n-2,or n-1 is referred and used by a certain time. The reference bitjudgement circuit 6 that generates the selected reference bit RSpractically determines whether each entry has been used.

[0054] In each entry, the information storage unit 1 is a storage area(storage element) storing information that should be originally stored.In the case of the TLB used for address conversion, the informationstorage unit 1 stores address information to be compared with a virtualaddress generated from the processor 30 (FIG. 2) and “addressinformation for replacement” used for replacement of the addressinformation. In the case of the data cache, the information storage unit1 stores address information to be compared with a physical addressgenerated from the processor 30 (FIG. 2) through the TLB and data bodyto be temporally held in the cache memory 8. The address information tobe compared with the generated physical address is an equivalent of anaddress of the main memory when the data is stored in the main memory.

[0055] The use status storage unit 2 is a register storing whether ornot the information in each of the entries 0, 1 . . . , n-2, and n-1 ofthe cache memory 8 has been actually used; the register being a kind ofmemory.

[0056] The selected reference bit RS stored in the selected referencebit storage unit 32 is determined through the reference bit judgementcircuit 6 based on information of an internal status value of the usestatus storage unit 2 composed of two bits or more for each of theentries 1, 2 . . . , n-2, and n-1 of the cache memory 8. For analgorithm of the internal status value stored in the use status storageunit 2, as described above, there is an example where the use status(used (hit)/unused (miss)) of each entry for certain past and currentperiods is stored and an example, where the number of times to use eachentry for a certain period is stored in a saturated counter. Herein, adescription will be given based on the example as to whether each entryhas been used for certain past and current periods is stored, withreference to FIG. 3.

[0057] The interval timer 3 is a circuit mainly composed of a counterthat measures an arbitrary period of time in accordance with the settingvalue of the control register 4 and generates the generation alternationsignal IS. Specifically, in order to manage the use status at certainintervals, a dedicated timer (time period measuring device) is used.This dedicated timer is referred to as the “interval timer 3.” In theinterval timer 3, operation specifications such as a setting of theperiod TI of the interval timer 3 is controlled by the setting value ofthe dedicated control register 4 as a kind of a memory which stores thesetting value. The control register 4 is a register and a kind of amemory allowing the operation of the interval timer 3, such as a periodto be controlled by software. The hit detection circuit 5 is a circuitthat compares processor cache access address information PA suppliedwhen the processor 30 accesses the cache memory 8, with cache addressinformation CA stored in the information storage unit 1 of each entry ofthe cache memory 8, and determines whether there is an entry having thecache address information CA, which agrees with the processor cacheaccess address information PA. When there is an entry having the cacheaddress information CA, which agrees with the processor cache accessaddress information PA, a hit signal HT is generated based on the numberof the entry. Moreover, in the use status storage unit 2 of thecorresponding entry, the internal status values of the first and secondreference bits RA and RB respectively stored in the first and secondreference bit storage units 37 and 38 are set to 1. As an example ofstoring the use status (used (hit)/unused (miss)) of each entry forcertain past and current periods, for each entry, the use status storageunit 2 is designed to include the first and second reference bit storageunits 37 and 38 to generate the status value of the reference bit R,which is stored in the reference bit storage unit 31.

[0058] For the internal status values of the first and second referencebits RA and RB respectively stored in the first and second reference bitstorage units 37 and 38, generation management is performed by thegeneration alternation signal Is generated from the interval timer 3. Inthe “generation management,” for each of the first and second referencebits RA and RB respectively stored in the first and second reference bitstorage units 37 and 38, a generation thereof is defined as “oldreference bit” or “current reference bit.”

[0059] Each of the first and second reference bits RA and RBrespectively stored in the first and second reference bit storage units37 and 38 is given a name such as “old (for a certain period)” or“current.” The first reference bit RA or the second reference bit RBdefined as “old” serves as a storage register that records and holds“the presence of a cache memory entry hit for a certain past period.”The first reference bit RA or the second reference bit RB defined as“current” serves as a storage register that records “the presence of acache memory entry hit for a certain period defined as “current.”

[0060] As shown in FIGS. 3 and 4, the definitions such as an “oldreference bit OLR” and a “current reference bit CRR” for the first andsecond reference bits RA and RB respectively stored in the first andsecond reference bit storage units 37 and 38 are switched based on thegeneration alternation signal IS generated by the interval timer 3.Specifically, if the internal status value of the first reference bit RAstored in the first reference bit storage unit 37 is defined as the “oldreference bit OLR,” and the internal status of the second reference bitRB stored in the second reference bit storage unit 38 is defined as the“current reference bit CRR” for a certain period, for the next period,the internal status value of the first reference bit RA is redefined asthe “current reference bit CRR” and the internal status of the secondreference bit RB is redefined as the “old reference bit OLR.” Thisoperation is repeated.

[0061] (Control Algorithm for First Reference Bit RA/Second ReferenceBit RB)

[0062] A description will be given of a control algorithm for the firstand second reference bits RA and RB with reference to FIGS. 2 and 3.FIG. 3 schematically shows transition of the internal status value ofthe first reference bit RA stored in the first reference bit storageunit 37 and the internal status value of the second reference bit RBstored in the second reference bit storage unit 38 by the generationalternation signal IS generated from the interval timer 3. In an initialstatus, the first reference bit RA is represented by CRR which means the“current reference bit,” and the second reference bit RB is representedas ORR which means the “old reference bit OLR.” These names are switchedby using the generation alternation signal IS of FIG. 2 as a triggersignal. Specifically, the status could be considered to change asfollows: when the generation alternation signal IS is sent, the internalstatus value of the first reference bit RA changes from the currentreference bit CRR to the old reference bit OLR. Next time the generationinterchange signal IS is sent, the internal status value of the firstreference bit RA changes from the old reference bit OLR to the currentreference bit CRR.

[0063] As shown in FIG. 3, when the generation alternation signal IS issent, the internal status value of the second reference bit RB changesfrom the old reference bit OLR to the current reference bit CRR. Nexttime the generation alternation signal IS is sent, the internal statusvalue of the second reference bit RB changes from the current referencebit CRR to the old reference bit OLR. In FIG. 3, the generationalternation signal IS is generated for each period TI of the intervaltimer 3. The reference bit R stored in each reference bit storage unit31 is a flag which records information as to whether the correspondingentry of the cache memory 8 is hit (a state wherein the entry isreferred and the contents of the cache memory 8 is used). As shown inFIG. 2, when the cache memory 8 is accessed and the hit detectioncircuit 5 determines that a “certain entry” of the cache memory 8 is hitby comparing the cache address information CA, which is provided fromthe translation information storage unit (address) 1 of each entry inthe cache memory 8 and the processor cache access address information(address value) PA, which is provided from the processor 30 in cacheaccess, the hit detection circuit 5 generates the hit signal HT. Thereference bit R stored in the reference bit storage unit 31 of the hitentry is set to 1. In this case, a bit set to 1 must be the referencebit R defined as “current reference bit CRR.” In this state, a bit ofthe reference bit R defined as the “old reference bit OLR” holds hitinformation of a period of a previous generation. When the internalstatus of the bit of the reference bit R that is the old reference bitOLR is changed to the current reference bit CRR status, the contentthereof is simultaneously reset to 0. When the internal status of thebit of the reference bit R that is the current reference bit CRR ischanged to the old reference bit OLR, there is no change and the samebit continues to hold the recorded hit information.

[0064]FIG. 4 shows a change of the status of the first and secondreference bits RA and RB, from which the selected reference bit RSstored in the selected reference bit storage unit 32 is generated alongthe time axis, and shows change of the contents thereof. As mentionedpreviously, the first and second reference bits RA and RB areinformation retained in the first and second reference bit storage units37 and 38 in the use status storage unit 2, respectively. FIG. 3 showsan example in which the entry is hit twice after a reset timing TR.Specifically, FIG. 4 shows how the internal status of the first andsecond reference bits RA and RB is changed by two hit signals as shownby entry hits Hit1 and Hit2 in FIG. 4. Immediately after the resettiming TR, the internal status value of the first reference bit RAbecomes the current reference bit CRR, and the internal status value ofthe second reference bit RB becomes the old reference bit OLR. Theinternal status values of the first and second reference bits RA and RBare initialized to 0. In such a state, first, when the first entry hitHit1 is received, the internal status value of the first reference bitRA, which is the current reference bit CRR, is set to “1” from “0” asshown by A in FIG. 4. The interval status of the second reference bit RBretains the status “0,” which is the internal status value in resetting.When the period TI of the interval timer 3 ends and the next generationalternation signal IS is received, the internal status value of thefirst reference bit RA is changed from the current reference bit CRR tothe old reference bit OLR, and the internal status value of the secondreference bit RB is changed from the old reference bit OLR to thecurrent reference bit CRR. The first reference bit RA stored in thefirst reference bit storage unit 37 maintains the recorded status of“1,” which is “information that the entry has been hit,” and the statusthereof is not changed until the internal status of the first referencebit RA becomes the current reference bit CRR.

[0065] Since the internal status value of the second reference bit RBstored in the second reference bit storage unit 38 is changed from theold reference bit OLR to the current reference bit CRR, the internalstatus value thereof is reset to “0” at the moment of the change.However, as shown by B in FIG. 4, since the internal status value of thesecond reference bit RB of the last generation is “0,” the secondreference bit RB does not change the status value of “0” until the nexthit signal is received.

[0066] When the entry hit Hit2 is received, since the internal status ofthe second reference bit RB stored in the second reference bit storageunit 38 is the current reference bit CRR, as shown by C of FIG. 4, theinternal status value of the second reference bit RB is set to “1” from“0.”

[0067] In this example, even if a plurality of hits are received, whenthe internal status value of the first reference bit RA stored in thefirst reference bit storage unit 37 or the internal status value of thesecond reference bit RB stored in the second reference bit storage unit38 that is the current reference bit CRR is “1,” the internal statusvalue is kept at “1” without change. If information of the number ofhits (frequency) is required, the method of using the first and secondreference bits RA and RB storing the use status (used (hit)/unused(miss)) of each entry for certain past and current periods is notemployed, instead the above described saturated counter is employed.

[0068] When the next generation alternation signal IS is received, asshown by D in FIG. 4, the internal status value of the first referencebit RA that had been the old reference bit OLR is changed to the currentreference bit CRR. Accordingly, the internal status value of the firstreference bit RA stored in the first reference bit storage unit 37 iscleared to “0” from “1” at the time of the change.

[0069]FIG. 5 shows only the reference bit judgement circuit 6, the hitdetection circuit 5, the use status storage unit 2, the interval timer3, a reference bit judgement control register 7, and the selectedreference bit storage unit 32 storing the selected reference bit RS,which constitute the cache memory system 50 according to the firstembodiment of the present invention. The area surrounded by a dottedline corresponds to the reference bit storage unit 31 shown in FIG. 2.

[0070] For a constitution of the use status storage unit 2 thatgenerates the selected reference bit RS stored in the selected referencebit storage units 32, various types can be employed. For example, thecache memory system in FIG. 5 includes the use status storage unit 2having a constitution of a 2-bit register 34, a 4-bit register 35 and a2-bit counter 9. The 2-bit register 34 includes the first and secondreference bit storage units 37 and 38. The 4-bit register 35 includesthe first reference bit storage unit 37, the second reference bitstorage unit 38, a third reference bit storage unit 39, and a fourthreference bit storage unit 40. The 2-bit counter 9 includes a counterhaving a 2-bit constitution. The reference bit judgement controlregister 7 is a register for software selection or setting of thedetermination algorithm that determines the conditions for setting theinternal status value of the selected reference bit RS stored in theselection reference bit storage unit 32 to “1” and “0” by filtering ofthe information of the use status storage unit 2. FIG. 6 shows anexample of use status storage unit 2 composed of the 2-bit register 34and the 4-bit register 35. FIG. 7 shows an example of use status storageunit 2 composed of the 2-bit register 34 and the 2-bit counter 9. FIG. 8shows an example of use status storage 2 composed of the 4-bit register35 and the 2-bit counter 9. In FIGS. 6 to 8, the constitution of theother parts is the same as that of FIG. 5. Note that an n-bit register(n: natural number) or an n-bit counter may be used instead of the abovedescribed 2-bit register 34 or the 2-bit counter 9. In this case, then-bit register includes, as a matter of course, n reference bit storageunits, or the n-bit counter includes a counter composed of n bits. Sinceat least two bits are required to judge the history, the 2-bit register34 is disclosed in FIG. 5. Also in FIGS. 6 to 8, the area surrounded bya dotted line corresponds to the reference bit storage unit 31 shown inFIG. 2.

[0071] (Reference Bit Determining Function and Random Entry SpecifyingFunction)

[0072] A description will be given of a generation method and adetermination function of each selected reference bit RS using theinformation of the first and second reference bits RA and RBrespectively stored in the first and second reference bit storage units37 and 38, the selected reference bit RS indicating whether thecorresponding entry is referenced in a certain generation. Furthermore,a description will be given of the method of randomly selecting an entryallowed to be updated.

[0073] As shown in FIG. 2, in the reference bit storage unit 31 of eachof the entries 0, 1, 2 n-2, and n-1 of the cache memory 8, the internalstatus of the first and second reference bits RA and RB, which existrespectively in the first and second reference bits RA and RB in the usestatus storage unit 2, is controlled by reception of the generationalternation signal IS, and generated from the interval timer 3. Thegeneration alternation signal IS is also sent to the reference bitjudgement circuit 6 from the interval timer 3. In the reference bitjudgement circuit 6, the internal status values of the first and secondreference bits RA and RB are precisely known, and it can be recognizedwhich of the first reference bit RA and the second reference bit RB isthe current reference bit CRR or the old reference bit OLR.

[0074] In the reference bit judgement circuit 6, the final informationvalue of the selected reference bit RS is determined by reflecting thehit status of the “old reference bit OLR” and the “current reference bitCRR” for each of the entries 0, 1, 2 . . . , n-2, and n-1. Morespecifically, as shown in FIGS. 5 to 8, the algorithm which generatesthe reference bit can be selected by a judgement control signal DCStransmitted from the reference bit judgement control register 7 to thereference bit judgement circuit 6.

[0075] For example, the internal status value of the selected referencebit RS is determined by only the information corresponding to thecurrent reference bit CRR (current generation) among the old referencebit OLR and the current reference bit CRR. Alternatively, the internalstatus value of the selected reference bit RS is determined byconsidering information of the entry hits Hit1 and Hit2 of twogenerations by taking a logic sum (OR) of the values of the oldreference bit OLR (last generation) and the current reference bit CRR(current generation). To the reference bit judgement circuit 6, not onlythe signal from the 2-bit register 34 composed of the first and secondreference bit storage units 37 and 38 is sent, but also the signal fromthe 4-bit register 35 can be sent. Further, the signal from the n-bitcounter can be sent to the reference bit judgement circuit 6. Theinformation of the selected reference bit RS can be determined byexamining the past hit status in more detail. As previously mentioned,the status value of the selected reference bit RS can be determinedaccording to the number of times that the entry is hit, which isrecorded using the saturated counter. Selection of the method largelydepends on the operating frequency of the circuit.

[0076] The entry having internal status value of the reference bit Rstored in the reference bit storage unit 31 of “0” is selected based onthe internal status value of the selected reference bit RS that is thusgenerated and stored in the selected reference bit storage unit 32.Since there is unlikely to be only one entry having internal statusvalue of “0,” among a plurality of the reference bit R, it is shown amethod of randomly selecting an entry from the entries having internalstatus of “0” is shown.

[0077] A description will be given of a case where the cache memory 8has 64 entries as an example. In FIG. 9, the area surrounded by a dottedline corresponds to the cache memory 8. As shown in FIG. 9, theseentries are divided into eight segments, for example. Specifically, asegment 0 includes the entries 0, 1, 2, 3, 4, 5, 6, and 7. A segment 1includes the entries 8, 9, 10, 11, 12, 13, 14, and 15. Similarly, asegment 6 includes the entries 48, 49, 50, 51, 52, 53, 54, and 55. Asegment 7 includes the entries 56, 57, 58, 59, 60, 61, 62 and 63. Eachdivided segment is considered as one segment since the entries aredivided such that one segment includes eight entries, and each segmentincludes eight reference bit storage units 31. Corresponding to theeight reference bit storage units 31, there are eight signals indicatingthe internal status values of the reference bits R. Note that, in FIG.9, an example of the cache memory 8 with 64 entries is shown, but thenumber of entries may be 32, 48, 128, 256, and so on. The number ofentries in one segment is not limited to eight.

[0078] [Entry Shuffle]

[0079] In the cache memory system 50 according to the first embodimentof the present invention, as shown in FIG. 10, a constitution forimplementing entry shuffle of the cache memory 8 includes the segmentseach being composed of i entries, the reference bit storage units 31, an8 to 8 selector 13A, a priority encoder 10A, and a NAND gate 15, and anentry shuffle counter 14. The respective reference bit storage units 31include the respective i reference bits R accompanying the respective ientries. The 8 to 8 selector 13A receives output signals from the ireference bit storage units 31. The priority encoder 10A receives ioutput signals from the 8 to 8 selector 13A and generates a selectedentry position number EPN. The NAND gate 15 receives the i outputsignals from the 8 to 8 selector 13A in a branching manner and generatesan unused entry presence signal EXS. The entry shuffle counter 14receives an entry shuffle signal ESH and generates an entry selectorcontrol signal ESC to the 8 to 8 selector 13A. In FIG. 10, the areasurrounded by a dotted line, which includes the 8 to 8 selector 13A, thepriority encoder 10A, and the NAND gate 15, corresponds to theprocessing circuit 12A.

[0080] As shown in FIG. 10, hardware in each segment is composed of theentries 0, 1, 2, 3, 4, 5, 6, and 7, which are arranged corresponding toentry position numbers EP from an LSB side to an MSB side, the referencebit storage units 31 that store the reference bits R contained in therespective eight entries, the 8 to 8 selector 13A, the entry shufflecounter 14, the priority encoder 10A, and the NAND gate 15. Adescription will be given based on the premise that each segmentincludes 8 entries as shown in FIG. 10. The internal status values ofthe respective reference bits R stored in the reference bit storageunits 31 of the respective entries are sent to the 8 to 8 selector 13A.The 8 to 8 selector 13A is used for entry shuffle in each segment.Specifically, after an entry in the segment is finally selected as atarget to be updated and then updated, the entry shuffle is performed.The 8 to 8 selector 13A includes eight inputs and eight outputs, and theinputs and the outputs are connected to correspond to each otherone-to-one. The 8 to 8 selector 13A is controlled by the entry selectorcontrol signal ESC supplied from the entry shuffle counter 14. The entryshuffle counter 14 functions as a backward counter. When the abovedescribed entry shuffle is performed, the entry shuffle counter 14changes an output status value on receiving the entry shuffle signalESH.

[0081] Giving a specific example, the output status value of the entryshuffle counter 14 is composed of a three bit signal. The 8 to 8selector 13A is switched in accordance with eight combinations of threebits of the signal. The output status value of the entry shuffle counter14 indicates, for example, a value equal to the position where the entry0 is located. Specifically, when the entry 0 is located at the positionof the entry position number EP=0, the output status value of the entryshuffle counter 14 is 0. When the entry 0 is located at the position ofthe entry position number EP=6, the output status value of the entryshuffle counter 14 is 6. When the output status value of the entryshuffle counter 14 is determined, the positions where the entries otherthan the entry 0 are connected are determined.

[0082] As shown in FIG. 10, the signals indicating the internal statusvalues of the reference bits R of the respective entries, which arepassed through the 8 to 8 selector 13A, are divided and transmitted tothe NAND gate 15 and the priority encoder 10A. The NAND gate 15 is acircuit for generating the unused entry presence signal EXS indicatingwhether there is an entry that is not hit in the segment. When at leastone of the internal status values of the reference bits R stored in thereference bit storage units 31 is “0,” the information of the unusedentry presence signal EXS becomes “1,” which indicates the presence ofthe entry that is not hit. The priority encoder 10A is a circuit thatselects the entries having internal status values of the reference bitsR as “0” and generates the position number of the entry that is closestto the MSB side from among the selected entries as the selected entryposition number EPN. The selected entry position number EPN does notindicate the number of the entry itself but the position where the entryis located. Next, a description will be given for the eight segments asa whole by putting together the segments each having the constitutionand mechanism as described above.

[0083] As shown in FIG. 10, in each segment, the selected entry positionnumber EPN indicating the position of the entry that is not hit, whichcan be a target to be replaced, is always generated for each segmentwhile reflecting the internal status value of the reference bit R storedin the reference bit storage unit 31 of each entry. Moreover, the unusedentry presence signal EXS indicating whether there is an entry that isnot hit in the segment is generated.

[0084] Summary of processing in the segment 0 is as follows. As shown inFIG. 11, the numeral of each of Entry 0, Entry 1, Entry 2, Entry 3,Entry 4, Entry 5, Entry 6, and Entry 7 indicates an entry number EN andcorresponds to each entry position number EP between the LSB (LeastSignificant Bit) and the MSB (Most Significant Bit). Each entry includesthe reference bit R stored in the reference bit storage unit 31, and theoutput from the reference bit R is sent to the processing circuit 12A.The processing circuit 12A is composed of the priority encoder 10A andthe EXS processing unit 11. The three bit output of the priority encoder10A indicates the selected entry position number EPN, and the output ofthe EXS processing unit 11 indicates the unused entry presence signalEXS.

[0085] As shown in FIG. 11, the 8 bit-signal indicating the internalstatus values of the reference bits R stored in the reference bitstorage unit 31 of the respective entries is passed through the priorityencoder 10A to encode the selected entry position number EPN, which isthe position number of the entry that is closest to the left end(referred to as the MSB side) from among the entries having internalstatus values of the reference bits which are “0.” The selected entryposition number EPN in this case is information (a number) indicatingthe position where the entry is located in the segment, but not thenumber of the entry itself.

[0086] In the segment 0, the signal indicating the presence of the entrywhose internal status value of the reference bit R is “0,” in otherwords, the signal indicated by the unused entry presence signal EXS isalso generated. The unused entry presence signal EXS, is an outputresulting from sending signal information of the internal status valuesof all the reference bits R stored in the reference bit storage units 31in each segment into the NAND gate 15 (FIG. 10).

[0087] For example, in the schematic view showing the processing in thesegment 0 of FIG. 11, when the internal status values of the referencebits R of the entries [7:0] are “11011011” (binary) from the upper side,the internal status values of the reference bits R of the entries 5 and2 are “0.” Accordingly, since these two entries are not hit, the entriesbecome the targets to be updated. Thus, the selected entry positionnumber EPN, which is the output of the priority encoder 10A becomes“101,” which is the position number “5.” The entry 5 (the positioninformation corresponds to the number of the entry itself) is offeredfrom the segment 0 as a candidate of the target to be updated. Herein,the unused entry presence signal EXS becomes “1.”

[0088] Other segments should be considered, but the description will becontinued focusing on the segment 0. When the entry belonging to thesegment 0 is finally selected as the updating entry, as shown in FIG.12, the entry (entry 0 in this example) on the LSB side, which has thesmallest position number (entry position number EP=0), is shifted to theposition of the entry (entry 7 in this example) on the MSB side, whichhas the largest position number (entry position number EP=7).Accordingly, as shown in FIG. 13, the entry 0 is shifted to the MSBside, the entry 7, the entry 6, the entry 5, the entry 4, the entry 3,the entry 2, and the entry 1 are sequentially shifted, and the entry 1is arranged on the LSB side. The reason for shifting the entry 0 on theLSB side to the entry 7 position on the MSB side in such a manner is toprevent the tendency of the entries with the larger entry numbers frombeing updated because of the priority encoder 10A basically used for theselection of the entry. For such a reason, the entry on the LSM side isshifted to the MSB side. FIGS. 12 and 13 illustrate the manner ofexecuting the entry shuffle in the segment to be updated. In thedescription of FIGS. 11 to 13, paying attention to the MSB side,disclosed is the example of shifting the entry on the LSB side to theMSB side, but paying attention to the LSB side, the entry on the MSBside may be shifted to the LSB side as a matter of course. Moreover, theEXS processing unit 11 may be set, not on the MSB side, but on the LSBside, and the unused entry presence signal EXS may be generated on theLSB side.

[0089] The entry shuffle of the cache memory 8 according to the presentinvention, (a) in a cache memory including a plurality of segments, eachbeing composed of a plurality of entries as a unit, includes the stepsof (b) sending the reference bit accompanied with each entry into theprocessing unit from the reference bit storage unit, and (c) performingthe entry shuffle by repeating the step of rotating the plurality ofentries and generating the selected entry position number and the unusedentry presence signal.

[0090] [Segment Shuffle]

[0091] In the cache memory system 50 according to the first embodimentof the present invention, as shown in FIG. 14, a constitutionimplementing segment shuffle of the cache memory 8 includes j segments,the unused entry presence signal (EXS) storage units 33, an 8 to 8selector 13B, a priority encoder 10B, an OR gate 17 and a segmentshuffle counter 16. The EXS storage units 33 include the respective junused entry presence signals EXS accompanied with the respective jsegments. The 8 to 8 selector 13B receives the j unused entry presencesignals. The priority encoder 10B receives j output signals from the 8to 8 selector 13B and generates a selected segment position number SPN.The OR gate 17 receives the branched j unused entry presence signals andgenerates an unused entry presence signal V. The segment shuffle counter16 receives a segment shuffle signal SSH and generates a segmentselector control signal SSC to the 8 to 8 selector 13B. In FIG. 14, thearea surrounded by a dotted line, including the 8 to 8 selector 13B, thepriority encoder 10B, and the OR gate 17, corresponds to the processingcircuit 12B.

[0092] Next, a description will be given of the segment shuffle withreference to FIGS. 15 to 17. As for the relationship between one segmentand the other seven segments in the segment shuffle, similar to the caseof the entry shuffle, the segments are processed by using the processingcircuit 12B, the priority encoder 10B and the rotate function containedin the processing circuit 12B.

[0093] The reference storage units 31 storing the reference bitsaccompanied with the respective entries in the entry shuffle arereplaced with the EXS storage units 33 storing the unused entry presencesignals EXS generated from the respective segments in the segmentshuffle. In other words, selection of the segment including theupdatable entry is intended to be made by sending the unused entrypresence signals EXS of the respective segments into the priorityencoder 10B of the processing circuit 12B. Herein, the segment includingthe target updating entry is selected based on information of theselected segment position number SPN indicating the position where theselected segment is located, and then the entry allowed for updating isfinally selected. The unused entry presence signal V in FIG. 15 is asignal indicating the presence of at least one entry allowed forupdating from among all of the entries. Herein, when the unused entrypresence signal V does not represent an effective signal, there is nounused (unhit) entry. Accordingly, the updating entry is actuallyrandomly selected.

[0094] When the segment including the updating entry is selected,similar to the entry shuffle in segments, rotation processing isperformed for the segments. The reason is the same as that in the entryshuffle. Specifically, as shown in FIG. 16, the segment (segment 0 inthis example) on the LSB side, which has the smallest segment positionnumber SP (segment position number SP=0), is rotated (shifted) to theposition of the segment (segment 7 in this example) on the MSB side,which has the largest segment position number (segment position numberSP=7). Accordingly, as shown in FIG. 17, the segment 0 is shifted to theMSB side, the segment 7, the segment 6, the segment 5, the segment 4,the segment 3, the segment 2, and the segment 1 are sequentiallyshifted, and the segment 1 is arranged on the LSB side. The reason forshifting the segment 0 on the LSB side to the segment 7 on the MSB sidein such a manner is to prevent the tendency of the segments with thelarger segment numbers from being updated because of the priorityencoder 10B (see FIG. 14) basically used for the selection of thesegment. For such a reason, the segment (segment with the smallestposition number) on the LSB side is shifted to the position of thesegment (segment with the largest position number) on the MSB side.FIGS. 16 and 17 illustrate the manner of executing the segment shuffle.Thus, the shuffle is performed in two processes for preparing the nextupdating operation. In the description of FIGS. 15 to 17, payingattention to the MSB side, disclosed is the example of shifting thesegment on the LSB side to the MSB side, but paying attention to the LSBside, the segment on the MSB side may be shifted to the LSB side.Moreover, in such a case, the unused entry presence signal V may begenerated on the LSB side.

[0095] The segment shuffle of the cache memory 8 according to thepresent invention, is (a) in a cache memory including a plurality ofsegments, each being composed of a plurality of entries as a unit,includes the steps of (b) sending the reference bits accompanied withthe respective entries into the processing circuit from the referencebit storage units, and (c) performing the entry shuffle by repeating thestep of rotating the plurality of entries and generating the selectedentry position number and the unused entry presence signal. In additionto the entry shuffle step, the segment shuffle of the cache memory 8includes the steps of (d) sending the unused entry presence signalaccompanied with each segment into the processing circuit from theunused entry presence signal storage unit and generating the selectedsegment position number and the unused entry presence signal, and (3)performing the segment shuffle by repeating the step of rotating theplurality of segments and generating the selected segment positionnumber and the unused entry presence signal.

[0096]FIG. 14 is a view showing the segments together. Specifically, asshown in FIG. 14, the entire hardware constituting the cache memorysystem according to the first embodiment of the present invention iscomposed of eight segments, the 8 to 8 selector 13B, the priorityencoder 10B, the OR gate 17, and the segment shuffle counter 16. Each ofthe segments includes the EXS storage unit 33 and a selected entryposition number (EPN) storage unit 41. The unused entry presence signalsEXS stored in the respective EXS storage units 33 of the respectivesegments are sent to the 8 to 8 selector 13B. The 8 to 8 selector 13B isused for shuffle of the segments. Specifically, after an entry containedin the segment is finally selected as a target to be updated and thenupdated, the segment shuffle is performed. Similar to the 8 to 8selector 13A shown in FIG. 10, the 8 to 8 selector 13A includes eightinputs and eight outputs, and the inputs and the outputs are connectedto correspond to each other, one-to-one. As shown in FIG. 14, the 8 to 8selector 13B is controlled by a segment selector control signal SSCsupplied from the dedicated segment shuffle counter 16. The segmentshuffle counter 16 is different from the entry shuffle counter 14 inFIG. 10 but similarly functions as a backward counter. When thepreviously mentioned segment shuffle is performed, the segment shufflecounter 16 changes an output status value thereof on receiving thesegment shuffle signal SSH.

[0097] Giving a specific example, the output status value of the segmentshuffle counter 16 is composed of a three it signal. The 8 to 8 selector13B is switched in accordance with eight combinations of three bits ofthe signal. This point is similar to the description in the entryshuffle counter 14 and the 8 to 8 selector 13A in FIG. 10. The outputstatus value of the segment shuffle counter 16 indicates, for example, avalue equal to the position where the segment 0 is located.Specifically, when the segment 0 is located at the position of thesegment position number SP=0, the output status value of the segmentshuffle counter 16 is 0. When the segment 0 exists at the position ofthe segment position number SP=6, the output status value of the segmentshuffle counter 16 is 6. When the output status value of the segmentshuffle counter 16 is determined, the positions where the segments otherthan the segment 0 are connected are determined. As shown in FIG. 14,each of the unused entry presence signals EXS stored in the EXS storageunits 33 is divided into two. One is transmitted to the OR gate 17, andthe other is transmitted to the 8 to 8 selector 13B.

[0098] The unused entry presence signals EXS which have passed throughthe 8 to 8 selector are transmitted to the priority encoder 10B. Theunused entry presence signal V indicates that at least one segmentincludes the entry that is not hit. The OR gate 17 is a circuit togenerate the unused entry presence signal V. When at least one of theunused entry presence signals EXS stored in the EXS storage units 33 is“1,” information of the unused entry presence signal V becomes “1,”which indicates the presence of the entry that is not hit.

[0099] The priority encoder 10B is a circuit that operates as follows.The priority encoder 10B selects the segments having signal statusvalues of the unused entry presence signals EXS which are “1” from theinternal status values of the unused entry presence signals EXS storedin the respective EXS storage units 33 of the eight segments. Asillustrated in FIGS. 15 to 17, the priority encoder 10B then generatesthe position number SP of the segment that is closest to the MSB side asthe selected segment position number SPN. The segment position numbersSP are not the number of the segments themselves, but the numbers of thepositions where the segments are located.

[0100] The result of the above operation provides the information aboutthe unused entry presence signal V corresponding to the information ofwhether there is an unused entry in all the entries and the informationof the selected segment position number SPN as the information of onesegment selected from the segments including the unused entry.

[0101] Simultaneously, as shown in FIG. 14, the information of theselected entry position number EPN can be obtained from each segment inthe EPN storage unit 41 as the information of one entry selected fromthe unused entries. Accordingly, when there is an updating request foran entry, the unused entry can be immediately selected based on thegiven information.

[0102] Since each selected segment position number SPN and each selectedentry position number EPN do not indicate the numbers of the segment orthe entry itself, the entry number EN is determined by a method shown asfollows. Herein, as an example, the constitution deriving the entrynumber EN uses subtracter circuits 24 and 25 as shown in FIG. 18.

[0103] First, a method of deriving the segment including the updatingentry is shown as follows. Specifically, referring to FIG. 18, thesubtracter circuit 24 is operated using a “value of the segment shufflecounter 16” as SSCNT and a “value of the selected segment positionnumber SPN” as SPN. The operation is expressed as follows.

0−(SSCNT−SPN)=SPN−SSCNT=USEL[2:0]  (1)

[0104] The result thereof is produced as a value of three bits andassumed to be USEL.

[0105] Next, a method of deriving the number of the target updatingentry in each segment is shown as follows. Specifically, referring toFIG. 18, the subtracter circuit 25 is operated using a “value of theentry shuffle counter 14” as ESCNT and a “value of the selected entryposition number EPN” as EPN. The operation is expressed as follows.

0−(ESCNT−EPN)=EPN−ESCNT=LSEL[2:0]  (2)

[0106] The result thereof is also produced as a value of three bits andassumed to be LSEL.

[0107] With the operations described above, the number of the selectedtarget updating entry is specified by six bits of the total of USEL andLSEL. Herein, USEL is on the high order side, and LSEL is on the lowerorder side. The entry number EN can be thus derived.

[0108] The method of generating the shuffle signals is as follows.Specifically, the segment shuffle signal SSH is generated immediatelyafter a certain entry is actually updated. Explaining the relationshipbetween updating the entry and execution of shuffle on the time axis, asshown in FIG. 19, the sequence of the operations are as follows withrespect to the arrow of a processing flow IF: updating demand RD,updating restart RR, updating end RE, and shuffle execution SHE.

[0109] As for the supply of the segment shuffle signal SSH, the segmentshuffle signal SSH is issued to the segment shuffle counter 16 each timethe segment shuffle is executed. As for the entry shuffle counter 14,the entry shuffle signal ESH is issued to the entry shuffle counter 14of the segment including the target updating entry. In this method, thesegment shuffle signal SSH is supplied to only the segment selected bythe value of USEL. For example, the segment shuffle signal is suppliedto the segment by sending the segment shuffle signal SSH and USEL[2:0]into a demultiplexer 18 as shown in FIG. 20. Specifically, when thesegment shuffle signal SSH and USEL[2:0] are sent to the demultiplexer18, a shuffle signal (segment 0) SSH0, a shuffle signal (segment 1) SSH1. . . , or a shuffle signal (segment 7) SSH7 is generated. Concretely,when USEL[2:0]=“0,” the segment shuffle signal SSH is supplied to onlythe segment 0. When USEL[2:0]=“1,” the segment shuffle signal SSH issupplied to only the segment 1. Similarly, when USEL[2:0]=“7,” thesegment shuffle signal SSH is supplied to only the segment 7.

[0110] In the case of a cache memory of the fully associative system,when the updating entry is selected, a method of randomly selecting theentry is used to avoid a complicated circuit design. Accordingly, thereis a possibility that the more frequently used entry may be updated. Incontrast, according to the cache memory and the updating method thereofof the present invention, the updating entry can be automaticallyselected from unused entries, so that time is not wasted and goodtemporal efficiency can be obtained.

[0111] According to the cache memory system of the present invention,since it is unnecessary to randomly select the entry to update the cachememory, it is unlikely that a more frequently used entry will beupdated, and the updating entry can be automatically selected from theunused entries. Consequently, a cache memory system with high efficiencycan be provided.

Second Embodiment

[0112] As described in the cache memory system according to the firstembodiment of the present invention, upon retrieval of the updatingentry, when the unused entry presence signal V does not represent aneffective signal, in other words, when there is no entry (unused) thatis not hit, the updating entry is actually and randomly selected. Whenthere is no entry that is not hit because the number of entries in cachememory 8, which the hardware provides for the operating environment ofthe software, is extremely few physically, the updating entry israndomly selected. The case where there is no entry that is not hitbecause the period TI of the interval timer 3 is extremely long, can behandled by setting the period TI of the interval timer 3 to be short.However, if all the mentioned operations are managed by the software,the amount of data handled becomes enormous.

[0113] In the cache memory system 51 according to the second embodimentof the present invention, the retrieval of the updating entry isautomatically performed by hardware. The cache memory system 51according to the second embodiment of the present invention includes thecache memory 8 and a count control mechanism provided by the intervaltimer 3. As shown in FIG. 21, the entire constitution is composed of thecache memory 8, an unused entry detection block 23, a count clockgeneration unit 21, a status register 22, the control register 4, theinterval timer 3, a lower boundary hit number register 19, and an upperboundary hit number register 20. The cache memory 8 is composed of theplurality of entries 0, 1 . . . , n-2, and n-1, the plurality ofinformation storage units 1 corresponding to the plurality of therespective entries and the reference bit storage units 31 storing therespective reference bits R accompanying the plurality of informationstorage units 1. As shown in FIG. 21, an unused entry presence signal(V) generation block 36 can be used instead of the upper boundary hitnumber register 20.

[0114] Similar to the cache memory system 50 according to the firstembodiment of the present invention shown in FIGS. 1 and 2, the intervaltimer 3 generates the generation alternation signal IS to the referencebit storage units 31 at the period TI of the interval timer 3 inaccordance with the control information CI set in the control register4. Similar to the first embodiment shown in FIG. 2, the generationalternation signal IS is used for generation management of the registerinformation constituting each reference bit storage unit 31. The clockCLK required for operating the interval timer 3 is supplied from thecount clock generation unit 21 in FIG. 21. The count clock generationunit 21 generates the clock CLK for operating the interval timer 3 at aperiod obtained by arbitrarily dividing the main clock supplied to theprocessor. The period of the clock CLK generated by the count clockgeneration unit 21 is actually controlled by a count clock controlsignal CCC generated from the unused entry detection block 23. Theperiod of the clock CLK for operating the interval timer 3, which isoriginally defined by hardware, can be adjusted to be lengthened orshortened with the count clock control signal CCC.

[0115] As shown in FIG. 21, the unused entry detection block 23 receivesan upper boundary hit number signal HUN from the upper boundary hitnumber register 20 or the unused entry presence signal V from the unusedentry presence signal generation block 36. Alternatively, the unusedentry detection block 23 also receives a lower boundary hit numbersignal HLN from the lower boundary hit number register 19 and transmitsthe count clock control signal CCC to the count clock generation unit21. The status register 22 is a storage element storing clock frequencyinformation CFI of the clock CLK generated from the count clockgeneration unit 21.

[0116] The frequency or the period of the count clock control signal CCCgenerated from the unused entry detection block 23 is determined in thefollowing manner. Specifically, it is determined whether the totalnumber of entries having internal status values of the reference bits Rstored in the reference bit storage units 31 are “1” is larger than acertain threshold or smaller than another certain threshold. When thetotal number is larger than the certain threshold (upper boundary hitnumber), the frequency of the count clock control signal CCC isincreased (the period is shortened). When the total number thereof issmaller than the certain threshold (lower boundary hit number), thefrequency of the count clock control signal CCC is reduced (the periodis lengthened).

[0117] Giving a concrete example, when the unused entry presence signalV from the unused entry presence signal generation block 36 is “0,”there is no unused entry so that the period TI of the interval timer 3is shortened. In other words, the period of the clock CLK generated bythe count clock generation unit 21 is shortened. In another method, whenthere is a lot of hit entries having internal status values of therespective reference bits R stored in the reference bit storage units 31that are “1” and the number of hit entries is larger than a certainthreshold (upper boundary hit number which is a value set in the upperboundary hit number register 20 in FIG. 13), similarly, the period ofthe clock CLK generated by the count clock generation unit 21 isshortened. When the number of hit entries having internal status valuesof the respective reference bits R stored in the reference bit storageunits 31 that are “1” is larger than the upper boundary hit number as avalue set in the upper boundary hit number register 20, as shown in FIG.21, the upper boundary hit number signal HUN is transmitted from theupper boundary hit number register 20 to the unused entry detectionblock 23.

[0118] In contrast, when there is a lot of missed entries havinginternal status values of the respective reference bits R stored in thereference bit storage units 31 that are “0,” in other words, when thereare a very few hit entries having internal status values of therespective reference bits R stored in the reference bit storage units 31that are “1” and smaller than a certain value (lower boundary hit numberwhich is a value set in the lower boundary hit number register 19 inFIG. 21), the period TI of the interval timer 3 is lengthened to observethe use status of the entry for a long period. When the number of hitentries having internal status values of the respective reference bits Rstored in the reference bit storage units 31 that are “1” is smallerthan the lower boundary hit number which is a value set in the lowerboundary hit number register 19, as shown in FIG. 21, the lower boundaryhit number signal HLN is transmitted from the lower boundary hit numberregister 19 to the unused entry detection block 23.

[0119] In the cache memory according to the second embodiment of thepresent invention, the flow chart based on a determination algorithm ofthe unused entry detection block 23 is composed of steps S1 to S5 asshown in FIG. 22.

[0120] (a) In step S1, the generation alternation signal IS is sent fromthe interval timer 3 to the reference bit storage units 31.

[0121] (b) Subsequently, the procedure proceeds to step 2. In step 2, itis determined whether the number of hit entries having internal statusvalues of the respective reference bits R stored in the reference bitstorage units 31 that are “1” is larger than the upper boundary hitnumber which is a value set in the upper boundary hit number register20.

[0122] (c) If the result of step 2 is YES, in step S5, the frequency ofthe count clock control signal CCC is increased to shorten the period TIof the interval timer 3. The procedure then returns to step S1.

[0123] (d) If the result of step 2 is NO, in step S3, it is determinedwhether the number of hit entries having internal status values of therespective reference bits R stored in the reference bit storage units 31that are “1” is smaller than the lower boundary hit number which is avalue set in the lower boundary hit number register 19.

[0124] (e) If the result of step 3 is YES, the procedure proceeds tostep S4. The frequency of the count clock control signal CCC is reducedto lengthen the period TI of the interval timer 3. Thereafter, theprocedure returns to step S1.

[0125] (f) If the result of step 3 is NO, the procedure returns to stepS1.

[0126] As described above, the period TI of the interval timer 3 isautomatically controlled in accordance with the number (hit number) ofused entries. Accordingly, in the cache memory system 51 according tothe second embodiment of the present invention, the function of randomlyselecting the unused entry can efficiently operate without fail.Moreover, even a case where the frequency of updating the cache by anapplication that varies with time can be flexibly and automaticallyhandled.

[0127] According to the cache memory system 51 of the present invention,software does not need to repeat the setting of the period TI of theinterval timer 3 frequently, and the period TI of the interval timer 3used for implementing the algorithm can be automatically adjusted.

Other Embodiments

[0128] As described above, the present invention has been described withthe first and the second embodiments, but it should not be understoodthat the description and the drawings as part of the present disclosuremay limit the present invention. Various alternations, examples, andoperational techniques will be apparent for those skilled in the artfrom the present disclosure. Accordingly, the technical scope of thepresent invention is determined by only the invention specific matteraccording to the scope of claims reasonable from the above description.

[0129] The cache memory system according to the embodiments of thepresent invention can be certainly applied to a general LSI orsemiconductor integrated circuit. The cache memory system can be appliedto a digital signal processor (DSP) for video/audio processing or customLSI that uses a cache memory of the fully associative system. Therefore,the cache memory system can be applied not only to a CPU or a timer LSI,but also to a general semiconductor integrated circuit or the like, thatuses a cache memory of the fully associative system.

[0130] The flowchart described in the embodiments of the presentinvention can be also certainly be applied to execution of a program.Furthermore, it is apparent that such a program can be provided by amedium storing the program, such as a ROM, a CD-ROM, and a CD-R/W.

[0131] According to the cache memory system, the cache memory, theupdating method for the cache memory system and for the cache memory,and the updating program of the cache memory system of the presentinvention, when updating the cache memory, provides a process in whichit is unnecessary to randomly select the entry. Accordingly, it isunlikely to update more frequently used entries, and the updating entrycan be automatically selected from the unused entries.

[0132] According to the cache memory system, the cache memory, theupdating method for the cache memory system and for the cache memory,and the updating program for the cache memory system of the presentinvention, the time period can be automatically adjusted by software,thus providing efficient use of time.

What is claimed is:
 1. A cache memory having a plurality of entries,wherein each of the entries comprises: an information storage unitconfigured to fetch and store a part of the information stored in a mainmemory; and a reference bit storage unit configured to store a usestatus for a certain period of information stored in the informationstorage unit.
 2. The cache memory of claim 1, wherein the reference bitstorage unit comprises: a use status storage unit configured to store ause status for a certain period of a reference bit corresponding to theinformation storage unit; a reference bit judgement circuit configuredto receive information stored in the use status storage unit; and aselected reference bit storage unit configured to store a selectedreference bit selected in the reference bit judgement circuit.
 3. Thecache memory of claim 2, wherein the use status storage unit comprises:a first reference bit storage unit configured to store a first referencebit; and a second reference bit storage unit configured to store asecond reference bit, wherein the first and second reference bit storageunits store use status for certain past and current periods of eachentry, respectively, and, for another period, stores the use status forthe certain current and past periods of each entry, respectively.
 4. Acache memory system comprising: a cache memory having a plurality ofentries, each of the entry include an information storage unitconfigured to fetch and store a part of the information stored in a mainmemory and a reference bit storage unit configured to store a use statusfor a certain period of information stored in the information storageunit; and a hit detection circuit connected to the information storageunits, the hit detection circuit configured to generate a hit signal toeach of the reference bit storage units.
 5. The cache memory system ofclaim 4, further comprising an interval timer connected to the referencebit storage units.
 6. The cache memory system of claim 4, wherein eachof the reference bit storage units further comprises: a use statusstorage unit configured to store a use status for a certain period of areference bit corresponding to each of the information storage units; areference bit judgement circuit configured to receive information storedin the use status storage unit; a selected reference bit storage unitconfigured to store a selected reference bit selected in the referencebit judgement circuit; and a reference bit judgement control registerconnected to the reference bit storage units.
 7. The cache memory systemof claim 5, further comprising a control register connected to theinterval timer.
 8. The cache memory system of claim 4, wherein the hitdetection circuit compares cache address information from each of theinformation storage units with processor cache access addressinformation from a processor and generates the hit signal to thereference bit storage unit.
 9. The cache memory system of claim 5,wherein the interval timer receives a control signal from the controlregister and generates a generation alternation signal to a use statusstorage unit and a reference bit judgement circuit, constituting each ofthe reference bit storage units.
 10. The cache memory system of claim 6,wherein the reference bit judgement circuit receives a judgement controlsignal from the reference bit judgement control register and generates afinal selected reference bit for each of the entries based on past andcurrent hit status.
 11. The cache memory system of claim 4, wherein theplurality of entries are assigned to a segment, the segment furthercomprises: a selector configured to receive output signals from therespective reference bit storage units of the plurality of entries; apriority encoder configured to receive output signals corresponding tothe plurality of entries from the selector and generates a positionnumber of a selected entry; a NAND gate configured to receive theplurality of output signals from the selector in a branching manner andgenerates an unused entry presence signal; an entry shuffle counterconfigured to receive an entry shuffle signal and transmits an entryselector control signal to the selector.
 12. The cache memory system ofclaim 4, wherein the plurality of entries are classified into aplurality of segments, each segment comprises: a plurality of theentries unused entry presence signal storage units, each of which storesthe unused entry presence signal accompanying each of the segments; aselector configured to receive the unused entry presence signal fromeach of the unused entry presence signal storage units; a priorityencoder configured to receive output signals corresponding to theplurality of segments from the selector and generates a position numberof a selected segment; an OR gate configured to receive the unused entrypresence signal in a branching manner and generates an unused entrypresence signal; and a segment shuffle counter configured to receive asegment shuffle signal and transmits a segment selector control signalto the selector.
 13. The cache memory system of claim 4, furthercomprising: an unused entry detection block connected to the referencebit storage units, respectively; an upper boundary hit number registerconnected to the unused entry detection block; a lower boundary hitnumber register connected to the unused entry detection block; a countclock generation unit connected to the unused entry detection block, thecount clock generation unit receiving a count clock control signal; anda status register connected to the count clock generation unit.
 14. Thecache memory system of claim 4, further comprising: an unused entrydetection block connected to the reference bit storage units,respectively; an unused entry presence signal generation block connectedto the unused entry detection block; a lower boundary hit numberregister connected to the unused entry detection block; a count clockgeneration unit connected to the unused entry detection block, the countclock generation unit receiving a count clock control signal; and astatus register connected to the count clock generation unit.
 15. Anupdating method for a cache memory, having a plurality of segments, onesegment including a unit of a plurality of entries, comprising: sendingreference bits accompanying the respective entries from reference bitstorage units into a processing circuit and generating a position numberof a selected entry and an unused entry presence signal; and performingentry shuffle by repeating rotating of the plurality of entries andgenerating the position number of the selected entry and the unusedentry presence signal.
 16. The updating method for a cache memory ofclaim 15, further comprising: sending the unused entry presence signalsaccompanying the respective segments from unused entry presence signalstorage units into a processing circuit and generating a position numberof a selected segment and an unused entry presence signal; andperforming segment shuffle by repeating rotating of the plurality ofsegments and generating the position number of the selected segment andthe unused entry presence signal.
 17. An updating method for a cachememory system, comprising: a process of sending a generation alternationsignal from an interval timer to a reference bit storage unit storing areference bit; a process of determining whether the number of hitentries is larger than an upper boundary hit number set in an upperboundary hit number register; a process of determining whether thenumber of hit entries is smaller than a lower boundary hit number set ina lower boundary hit number register when the number of hit entries isnot larger than the upper boundary hit number; a process of shortening aperiod of the interval timer when the number of hit entries is largerthan the upper boundary hit number; and a process of lengthening theperiod of the interval timer when the number of hit entries is smallerthan the lower boundary hit number.
 18. An updating program for a cachememory system to be executed by a cache memory system configured toinclude an unused entry detection block connected to a reference bitstorage unit constituting a cache memory; an interval timer; an upperboundary hit number register connected to the unused entry detectionblock; and a lower boundary hit number register, comprising: aninstruction to send a generation alternation signal from the intervaltimer to the reference bit storage units; an instruction to determinewhether the number of hit entries is larger than an upper boundary hitnumber set in the upper boundary hit number register; an instruction todetermine whether the number of hit entries is smaller than a lowerboundary hit number set in the lower boundary hit number register whenthe number of hit entries is smaller or equal to the upper boundary hitnumber; an instruction to shorten a period of the interval timer whenthe number of hit entries is larger than the upper boundary hit number;and an instruction to lengthen the period of the interval timer when thenumber of hit entries is smaller than the lower boundary hit number. 19.An updating program product stored on a memory medium of a cache memorysystem to be executed by a cache memory system configured to include, anunused entry detection block connected to a reference bit storage unitconstituting a cache memory; an interval timer; an upper boundary hitnumber register connected to the unused entry detection block; and alower boundary hit number register, comprising: an instruction to send ageneration alternation signal from the interval timer to the referencebit storage unit; an instruction to determine whether a number of hitentries is larger than an upper boundary hit number set in the upperboundary hit number register; an instruction to determine whether thenumber of hit entries is smaller than a lower boundary hit number set inthe lower boundary hit number register when the number of hit entries issmaller or equal to the upper boundary hit number; an instruction toshorten a period of the interval timer when the number of hit entries islarger than the upper boundary hit number; and an instruction tolengthen the period of the interval timer when the number of hit entriesis smaller than the lower boundary hit number.